Adder with high efficiency and accuracy is the major requirement for electronic circuit design. Here the optical logic gate based adder circuit is designed for better performance analysis of optical input signals varied with the wavelength. Efficiency of the adder can be improved by increasing the speed of operation, reducing the complexity and power consumption. To maintain the high efficiency with accuracy, a new combination of adder has been proposed and tested in this work. A new adder by combining the logics of

Advanced cutting-edge technologies focus has shifted to the optical domain because of its faster rate and lack of electromagnetic interference. Networks of optical splitters, switches, circulators, and many more require the ability to switch at extremely high speeds. Because of the need for electro-optic conversions, the performance of optical networks has been hampered by the employment of virtual gates. That is why photonic networks will benefit from optical signal processing and computing technologies by forcing logic gates to operate exclusively in optical mode. To increase an all-optical network, optical gadgets are the simple requirement. In case of optical gadgets, the signals stay within the photonic model, thereby putting off the digital bottleneck. Consequently, the speed of the gadget can reach up to tera hertz (THz). Therefore, the work prefers to design the optical logic gate-based adder circuit. Adders are the important elements in the application of filters and arithmetic and logic unit (ALU) of processors and computers. Further, adders play a major role in computers for calculation of addresses and other operators like program counter for processing. Initially processors processed a smaller number of bits for all kind of applications. The extraordinary growth in technology forces the designers to go for multiple numbers of bits processing especially in high level applications of optical communication. Hence, adders for multiple bit processing are an important requirement for any circuit which uses it. And for adding multiple numbers of bits, ripple carry adder, carry look ahead adder, carry select adder, carry skip adder, carry save adder and parallel prefix adder with high speed operation is used by the designers. Less area utilisation, faster computation or less delay, minimum fanout or less complexity and low power consumption are the important parameters to be noted for a better adder. Parallel prefix adder with minimum complexity, minimum delay and power consumption is the most needed parameters to be considered for the effective design of high speed circuits.

From the detailed study on the six important parallel prefix adders that had been designed and tested earlier for addition applications, it is observed that, reduction in the time consumption has been successfully tested form the implementation of Sklansky Adder (SA) [

From the detailed survey, it is clear that, all the existing adders are efficient in any one or two aspects and there is no adder available to perform well in all the three important aspects, that is, power reduction, area reduction and delay reduction. And the desperate need of optical logic gate based adder for optical communication related applications. If any single adder logic or modified single adder logic or combination of any two or three logics to form new adder logic can perform the above said aspects and to produce the accurate results, then it can be further used to design important electronic circuits like multipliers, filters and arithmetic units.

Accuracy is the most important factor to be considered while study, design and examine any adder to be utilised in such electronic circuits. Improvement in the speed of operation, power consumption and the size reduction are the main factors to be considered while looking for the better accuracy. Parallel prefix adders are the one satisfying the above factors. But they are not able to satisfy the complexity issues while they are handling more number of input bits.

To overcome the complexity issues and to retain the higher accuracy, new adders are required. One such adder is the combination of logics of Brent Kung, Sklansky and Kogge Stone (BSK). This new combination has a structure which handles more input bits with less complexity. To achieve the above requirement, the structure has been modelled with tree grafting technique. That is, first two stages are formed by grafting the logic of Brent Kung adder with Sklansky adder and the latter stage is formed by grafting the logic of Kogge Stone adder to the initial stages and named as BSKTGT Adder (BSKTGTA).

After the detailed survey about the structures and efficiency of the existing adders, the new adder has been proposed by combining the structures of the three important and efficient adders. This new combination utilises grey and black cells in an effective way to reduce the complexity.

Optical logic gate-based circuit permits direct parallel switch from an optical processor or storage detail to a widespread electronic gadget. The optical enter beams can be viewed as control indicators or as logical inputs that growth the gadget complexity and permit direct interplay of the digital common-sense circuits with the optical beam states. To support the optical based communication system module design, the proposed adder design is very much needed. Design of any adder consists of three basic processing stages. They are pre-processing: first stage of an adder and it consists of two sub stages named propagate and generate, carry network: the second stage of an adder and it consists of carry propagation and generation and post-processing: the third stage of an adder and it consists of XOR gates for producing the results sum and carry. This processing stage has been increased further for handling a greater number of input bits as per the new design requirements of any adder. That is, the number of stages will increase for increase in input bits. Here, this proposed method utilises the same three stages with a special capability of handling any number of input bits only by three stages. The processing has been described with eight equations as follows.

Pre–Processing Stage:

The generate bit is_{i}–is the i^{th} first input bit and b_{i}–is the i^{th} second input bit.

Carry Network:

Grey cell is_{i−1}–is the previous generate bit and g_{c}g_{j–}j^{th} is the gray cell generate bit.

and for black cell is_{c}g_{j}–is the j^{th} black cell generate bit._{c}p_{j}–is the j^{th} black cell propagate bit.

Post–Processing Stage:

From

From _{i}–is the i^{th} sum bit and c_{i−1}–is the last stage of generate bit in grey cell and black cell and for carry,

where, b_{c}g_{j–}last j^{th} black cell generate bit.

The stages of proposed adder have been constructed by considering the above equations. And the process flow is shown in

The first stage has been modelled with Sklansky adder and it is almost similar to that of Brent Kung adder’s first stage. The second stage functions with the logic of Kogge Stone adder with the routing logic similar to that of Sklansky adder. And the final stage functions with the Kogge Stone logic alone. First two stages are supported by Sklansky logic even though they are physically Brent Kung and Kogge Stone respectively. This combination along with Kogge Stone logic in the final stage provides a new combination with new structure and named as BSKTGTA. This new combination of adder has only three stages for any number of bits. This is one of the main advantages of proposed this BSKTGTA and it can be utilised for larger number of input handling applications. This work includes the design and comparison of 8 bit, 16 bit and 32 bit adders. Structure of 4 bit BSKTGT adder is given in

With the help of four bit logic, the structure of proposed 32 bit BSKTGT adder has been designed and given in

The complete adder is a logic device that performs the addition of three binary digits. In a cascade of adders, it adds eight, sixteen, or 32-bit binary values in a sequential manner. Stages A, B, and C of a one-bit full adder add three one-bit values together with operands A and B and a-bit carried over from the previous much less significant degree. From

From

Name of the adder | Stages | Cell count from the structure | ||
---|---|---|---|---|

Black cell | Grey cell | Buffer | ||

KSA [ |
98 | 31 | ||

BKA [ |
08 | 47 | ||

HCA [ |
06 | 49 | 31 | 35 |

SA [ |
49 | 31 | 48 | |

LFA [ |
06 | 32 | 31 | 42 |

KA [ |
83 | 31 | ||

Proposed BSKTGTA |

From

To verify the operation, two 32 bit data (FFFFFFFF and AAAAAAAA) have been given as input for all the adders discussed in this work. And the result shows that all the adders have performed the same addition operation with the resulted Sum: AAAAAAA9 and Carry: 1. The simulated waveform of proposed BSKTGT adder is given in

All the adders taken for the analysis in this work have been synthesised by using Cadence platform with 45 nanometre (nm) technology and the performance have been tested by measuring the area utilisation, power consumption, propagation delay, power delay product (PDP) and the cell count. The resulted values are tabulated in the following section.

Name of the adder | 8–bit | 16–bit | 32-bit | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|

Power (μW) | Delay (pS) | PDP (fJ) | Area | Cell count | Power (μW) | Delay (pS) | PDP (fJ) | Area | Cell count | Power (μW) | Delay (pS) | PDP (fJ) | Area | Cell count | |

KSA [ |
13462.501 | 1188 | 15.99345 | 193.92 | 50 | 34773.288 | 1475 | 51.2906 | 494.240 | 130 | 82548.908 | 1951 | 161.0529 | 1173.621 | 290 |

BKA [ |
10962.459 | 1525 | 16.71775 | 154.87 | 38 | 25585.651 | 2184 | 55.87906 | 340.034 | 84 | 54173.877 | 2878 | 155.9124 | 685.159 | 146 |

HCA [ |
11284.655 | 1382 | 15.5954 | 161.20 | 40 | 27539.753 | 1700 | 46.81758 | 379.445 | 96 | 61588.885 | 2001 | 123.2393 | 839.004 | 192 |

SA [ |
11322.326 | 1298 | 14.69638 | 161.56 | 40 | 27961.271 | 1784 | 49.88291 | 383.057 | 96 | 63799.665 | 2523 | 160.9665 | 850.560 | 192 |

LFA [ |
10916.214 | 1525 | 16.64722 | 154.51 | 38 | 25820.464 | 1923 | 49.65274 | 346.723 | 86 | 55582.597 | 2423 | 134.6766 | 727.098 | 158 |

KA [ |
13462.501 | 1188 | 15.99345 | 193.92 | 50 | 34757.984 | 1654 | 57.4897 | 493.879 | 130 | 82796.076 | 2045 | 169.3180 | 1173.260 | 290 |

BSKTGTA | 10753.647 | 1484 | 15.95842 | 149.86 | 36 | 23851.341 | 1846 | 44.02957 | 334.475 | 78 | 52512.624 | 2336 | 122.6695 | 631.191 | 132 |

From

Name of the design | KSA [ |
BKA [ |
HCA [ |
SA [ |
LFA [ |
KA [ |
Proposed BSKTGTA |
---|---|---|---|---|---|---|---|

Area utilised | 1173.621 | 685.159 | 839.004 | 850.560 | 727.098 | 1173.260 | 631.191 |

From

Name of the adder | Power consumption | ||
---|---|---|---|

Leakage power in nano watts (nW) | Dynamic power in nano watts (nW) | Total power in micro watts (μW) | |

KSA [ |
24.829 | 82524.079 | 82.548908 |

BKA [ |
15.416 | 54158.461 | 54.173877 |

HCA [ |
18.423 | 61570.462 | 61.588885 |

SA [ |
18.423 | 63781.242 | 63.799665 |

LFA [ |
16.200 | 55566.396 | 55.582597 |

KA [ |
24.829 | 82771.247 | 82.796076 |

Proposed BSKTGTA | 14.091 | 52498.533 | 52.512624 |

From

Name of the design | KSA [ |
BKA [ |
HCA [ |
SA [ |
LFA [ |
KA [ |
Proposed BSKTGTA |
---|---|---|---|---|---|---|---|

Delay measured (pS) | 1951 | 2878 | 2001 | 2523 | 2423 | 2045 | 2336 |

From

Name of the adder | Power delay product (PDP) | ||
---|---|---|---|

Total power in micro watts (μW) | Delay in pico seconds (pS) | PDP in femto Joule (fJ) | |

KSA [ |
82.548908 | 1951 | 161.0529 |

BKA [ |
54.173877 | 2878 | 155.9124 |

HCA [ |
61.588885 | 2001 | 123.2394 |

SA [ |
63.799665 | 2523 | 160.9666 |

LFA [ |
55.582597 | 2423 | 134.6766 |

KA [ |
82.796076 | 2045 | 169.3180 |

Proposed BSKTGTA | 52.512624 | 2336 | 122.6695 |

From

Name of the design | KSA [ |
BKA [ |
HCA [ |
SA [ |
LFA [ |
KA [ |
Proposed BSKTGTA |
---|---|---|---|---|---|---|---|

Cell count | 290 | 146 | 192 | 192 | 158 | 290 | 132 |

The proposed BSKTGTA performed well in adding any 8, 16 and 32 bit values. From the results discussed, it is clear that the proposed adder has consumed 52.512426 μW which saves 3.16% of power when comparing to the Brent Kung adder which is the next best adder with the power consumption of 54.173877 μW. Similarly, the BSKTGTA utilised the area of 631.191 which is 8.55% less when comparing to the next best KSA with the area of 685.159, BSKTGTA has the cell count of 132 which is 10.61% reduction in the cell count when comparing with the next best BKA with the cell count of 146. The PDP value of proposed BSKTGTA is 122.6695 fJ, which is 0.46% less than that of the next best HCA with the PDP value of 123.2394 fJ. Further, this optimized design can be used in optical communication based applications for the replacement of existing adder and can also handle any number of input bits with the same logic.