Low Power circuits play a significant role in designing large-scale devices with high energy and power consumption. Adiabatic circuits are one such energy-saving circuits that utilize reversible power. Several methodologies used previously infer the use of CMOS circuits for reducing power dissipation in logic circuits. However, CMOS devices hardly manage in maintaining their performance when it comes to fast switching networks. Adiabatic technology is employed to overcome these difficulties, which can further scale down the dissipation of power by charging and discharging. An Efficient Charge Recovery Logic (ECRL) based adiabatic technology is used here to evaluate arithmetic operations in circuits like inverter, full adder, Carry Look-Ahead adder etc. A better chance at reducing delay in digital circuits is illustrated by developing a Kogge-stone Adder, built using the ECRL technology. The developed circuitry is further integrated into a Fast Fourier Transform (FFT), which demonstrates the circuit’s enhancement into DSP applications. Not only does this design reduce delay in VLSI switching circuits, but also narrows the power dissipation down to a minimum. This technique proved superior to the existing PFAL technique by demonstrating almost 10% less power dissipation with minimal propagation delay. All the circuits have been simulated at 45 nm technology using the Tanner EDA tool.

Designing techniques for low power consumption have vastly influenced the current electronic industry trend, due to the increasing demand for compact gadgets such as cellphones, laptops, and several other handheld devices. The microelectronics industry have immensely evolved since transistors were initially designed, which set forth the foundation for such devices. A large number of gadgets were designed by integrating several transistors in them. As the current portable devices necessitate a huge number of logic gates to assemble in a single integrated chip, the area (or) the size of the chip becomes a major concern. Presently, a single IC incorporates fabrication of around 100,000 or even more transistors in it, thusly calling it VLSI (very large scale integration) [

This work makes use of the ECRL logic to build full adders and develop Kogge-Stone as well as multiplier circuits using the adder. Kogge-Stone is another VLSI architecture that employs minimum chip size and adiabatic method to improve power dissipation in devices. By cascading the architectures of multiplexer and Kogge-Stone circuits, the product can be pitched as a DSP application. The flow for the proposed work has been given in the following

Basic implementations of several full-adder cells have been designed with modified logic styles, some of which have been compared with this work. Although they possess a similar functionality where intermediate nodes and outputs are created, the loads inside them have been changed. Several designs favour a single performance aspect at the cost of others. In some devices, full adders are created out of a single logical design whereas some designs possess multiple [

The remaining sections have been detailed as shown: Section 2 describes the related work regarding the description of ECRL Logic. Section 3 describes the proposed work of this paper. The outcomes explaining the power dissipation and the transistor count has been reported in Section 4. In Section 4, conclusions have been drawn.

The proposed work concentrates on designing Kogge-stone adder and multiplexer circuits and further enhance it into an FFT application, by using ECRL. This is performed by initially developing a full adder, ripple carry adder and Carry Look-Ahead Adder with this technology. This operation makes use of 4-bit functionality. The multiplexer minimizes the mux stages using the variable adder length feature and thus lowers the critical path. This in turn decreases the power dissipation of the circuit. This circuit will be developed into a device that can prove to be an efficient power-consuming candidate for DSP applications. ECRL is introduced in this paper by initially discussing adiabatic logic and its significance in adders.

Adiabatic, described from a thermodynamics process, illustrates that energy is not exchanged to the external environment, thereby stating that there will not be any chance of power or energy to dissipate. Adiabatic logic is beneficial in the switching process since power is not dissipated as heat energy through the resistor present there. It instead recycles back the power to the supply from the load capacitance, and the same energy (or) power is used for the next operation. The energy is recovered without any loss in the system and the heat is preserved. The energy is stored in load capacitors, in which the grounded charges will be recycled back to the power clock. Some of the various adiabatic techniques used in this paper have been explained below.

Here, the pre-charge and evaluation phases are performed at the same time by eliminating the pre-charge diode and dissipating the energy at the same time, as compared to other adiabatic circuits. The proposed ECRL comprises two cross-coupled PMOS transistors and two NMOS transistors as N-functional blocks. The full swing output is obtained in both the pre-charge and recovery phase because of the two cross-coupled PMOS transistors.

The pre-charge and recover phases deliver complete output swings, owing to the presence of the cross-coupled PMOS transistors. However, when the threshold voltage of PMOS is attained by the supply clock voltage, the device turns off. Hence, the recovery path connecting to the clock comes about disconnected [

The full adder logic takes in eight inputs, generating an adder that is a byte-wide, and adds a carry bit from one adder to the other. Full adder is implemented by making use of the ECRL, instead of the basic CMOS logic.

A power clock initiates the logic to operate in four various phases: Wait, Evaluate, Hold and Recover.

Wait: the previous gate provides the input signal.

Evaluate: stability of input signal is maintained.

Hold: input kept at hold, meanwhile it is reduced, thereby keeping the supply voltage constant.

Recover: “V_{DD}” comes to zero position and becomes lower, and energy from the output node is recovered.

Recently, designers are considering important issues like high speed, small silicon area and low power consumption for developing digital circuits. The popular methodology among computational logic elements is binary addition. The carry look-ahead adder is also known as “

The carry and sum outputs are

Implementing this logic facilitates the transfer of some of the charges to the ground, thereby recovering part of the energy. The two PMOS transistors help to pull the power back to the AC supply. The summing circuit for the ECRL based CLAA circuit is shown in

In addition to the performance of the CLAA, a Parallel Prefix Adder is developed for attaining better performance than other adders. It uses binary addition just like Carry look-ahead. Kogge-Stone adder is known as the fastest adder available, and a large number of recurrence problems are dealt with in this adder. Fig. shows the structure of Kogge-Stone adder circuit.

A multiplexer circuit is implemented along with CLAA. Generally, CLAA and Ripple Carry Adder (RCA) will be used to operate the multiplexer function. Here since ECRL logic is used, only CLAA will be required for developing the circuit. In this following structure, the length of the adder will be variable for reducing the number of multiplexer stages which reduces the critical path, and eventually the power dissipation.

SDF utilizes the register more effectively by storing each output of the butterfly model inside the feedback shift registers. The Radix-4 butterfly comprises four inputs and outputs. The radix-4 FFT requires only 75% as many complex multiplies as the radix-2 FFTs, although it uses the same number of complex additions. These additional savings make it a widely-used FFT algorithm.

A representation of several circuits designed using the Tanner EDA tool is depicted in the following sections. A full adder, Ripple Carry Adder (RCA), Carry Look-Ahead Adder (CLAA) is developed using the proposed ECRL technique. The obtained results are compared with the conventional CMOS logic based respective circuits and attained much better and higher power dissipation values.

The outcomes of the proposed RCA circuit in ECRL technology had been simulated using 45 nm technology, in the Tanner EDA tool. Tanner EDA tool Software. When a = 0, b = 0, and c = 0, the obtained sum will be “0” and C_{out} is “0”. Whereas when a = 1, b = 1, and c = 1, the obtained sum will be “1” and C_{out} is “1”. Based upon the operation, the obtained Power Dissipation is 0.25 μW. A schematic representation in the Tanner EDA tool is shown in

When a = 0, b = 0, and c = 1the obtained sum is “1” and C_{out} is “0”. When a = 0, b = 1, c = 1, the obtained sum is “0” and C_{out} is “1”. Whereas for the conventional CMOS logic, the obtained Power Dissipation is 0.79 μW.

The ECRL-based Carry Look-Ahead Adder Circuit is also simulated by employing the 45 nm technology, in Tanner EDA tool. The Power Dissipation of CMOS Carry Look Ahead Adder is 6.0038 nW. The simulation result of ECRL-based Carry Look-Ahead Adder Circuit had been simulated by using 45 nm technology, mentor graphics EDA tool Software. The schematic of the CLAA based Kogge-Stone circuit is represented in

The output waveform for the ECRL based Kogge-Stone circuit developed using Carry Look-Ahead Adder is shown in

Propagation delays in the circuits can be further reduced by implementing multiplexers in the circuit. The complexity that goes into designing each logic gate can be efficiently suppressed by employing 2-1 multiplexers. MUX benefits from universal gate status, as any kind of gate can be executed using this. When provided with real and inverted inputs, it produces both real and inverted outputs. In the above circuit, the XOR gate at the final stage has been replaced with a 2-1 MUX, shown in

The Finite Fourier Transform (FFT) is implemented using the KSA with the help of a radix 4 SDF as explained in Section 3. The developed circuit of the FFT using the ECRL based Kogge-stone adder is given in

Circuit | Technique | Power dissipation |
---|---|---|

Inverter | CMOS | 8.873 μW |

ECRL (proposed) | 7.783 μW | |

Ripple carry adder | CMOS | 0.78 μW |

ECRL (proposed) | 0.25 μW | |

Full adder | CMOS | 0.8 μW |

ECRL (proposed) | 0.065 μW | |

Carry look-ahead adder | CMOS | 59.28 nW |

ECRL (proposed) | 6.0038 nW |

Circuit | Technique | Number of transistors | Number of load capacitors |
---|---|---|---|

ECRL sum | CMOS | 28 | - |

ECRL (proposed) | 22 | - | |

ECRL carry | CMOS | 20 | - |

ECRL (proposed) | 14 | - | |

ECRL-based full adder | CMOS | 0.8 μW | 37 F |

ECRL (proposed) | 0.065 μW | 28 F |

Circuit | Technique | Components | Propagation delay (ns) |
---|---|---|---|

Ripple carry adder | CMOS | Multiplier, 4 full adders | 9.332 |

ECRL (proposed) | Four full adders | 7.894 | |

Kogge-stone using CLAA | CMOS | Multiplier, 1 KSA | 7.881 |

ECRL (proposed) | 1 KSA using 4 CLAAs | 6.378 | |

Kogge-stone and MUX | CMOS | 1 KSA | 5.439 |

ECRL (proposed) | 1 KSA | 3.228 |

This paper reports on the energy conservation of ECRL-based Kogge-stone adder circuits for DSP applications like Fast Fourier Transform (FFT). By utilizing minimum transistors and designing full adder and Carry Look-Ahead adder circuits using ECR logic, a reduced power dissipation was obtained in the range of nanowatts (nW). This adiabatic technology employs recharging functionality and develops an effective power dissipation factor. This methodology decreases the propagation delay in fast switching circuits, as a result of which the device becomes even cost economic. A multiplexer is also designed with the carry look-ahead adder, which benefits from variable adder length, making the number of multiplexer stages to a minimum. Comparison is performed for the proposed inverter, ripple carry adder, full adder and carry look-ahead adders with their corresponding CMOS based circuits. The comparison depicted a much-reduced power dissipation from the adiabatic logic, which makes it a compatible device and core contender for high-performance DSP applications like modem concentrators, cellular base stations etc. A Finite Fourier Transform (FFT) architecture is constructed using the KSA structure with the help of a Radix 4 format. Minimal power dissipation of 6.0038 nW is attained for the proposed design with a reduced propagation delay of around 3 ns.