Recent advances in the development of image denoising applications for eliminating the various sources of noise in digital images have employed hardware platforms based on field programmable gate arrays for attaining speed and efficiency, which are essential factors in real-time applications. However, image denoising providing for maximum denoising performance, speed, and efficiency on these platforms is subject to constant innovation. To this end, the present work proposes a high-throughput fixed-point adaptive edge noise filter architecture to denoise digital images with additive white Gaussian noise in realtime using a nonlinear modified pixel-likeness weighted-frame technique. The proposed architecture works in two stages. The first stage involves normal and conditional sorting. The second stage is a decision-oriented output selection unit. Decision-oriented adaptive windowing is included for better impulse noise suppression and edge preservation. The denoising performance of the proposed denoising scheme is demonstrated to be superior to those currently available state-of-the-art approaches. Moreover, the power consumption is reduced by 25.01% compared to conventional algorithms.

The Discrete Wavelet Transform (DWT) of a noisy image includes a substantial number of factors with low SNRs, and shrinking the wavelet coefficients associated with these DWT factors with low Signal to Noise Ratio (SNRs) was demonstrated to be a useful procedure for denoising images, particularly those with additive white noise. In addition to digital images, the good performance of DWT-based denoising strategies has made these strategies useful for speech signals, electrocardiograms (ECGs), and encephalograms [

To this end, the present work proposes continuous use of the forward/backward pixel likeness weighted frame (PLWF) technique for image denoising. The proposed method is planned and executed on an FPGA platform utilizing the Xilinx System Generator (XSG), MATLAB 2017a, and the XUP Vertex-II Pro improvement board. The Pixel Likeness Weighted Frame (PLWF) is employed in conjunction with a modified Adaptive Edge Noise (AEN) filter to minimize noise such as salt-and-pepper and Gaussian noise [

A block diagram of the proposed PLWF image denoising algorithm is presented in

A. Line buffers

The proposed algorithm employs a 3 × 3 convolution mask. Therefore, the computation is facilitated by four hybrid multiplexers and two line buffers, where the odd and even line buffers store pixels at odd and even column positions, respectively. The cost and power consumption of the implementation are reduced by adopting a double-port SRAM in the line buffers to conduct the computational activity [

B. Register bank

The register bank consists of 12 registers, Reg0 to Reg11, that accumulate the 3 × 3 pixel estimates of the present convolution masks. The architecture of the line buffers and register bank are illustrated in

C. Threshold block

The threshold block design is illustrated in

D. Adaptive edge noise filter

The two-stage pipeline design of the AEN filter is illustrated in

A flowchart of the proposed PLWF algorithm is presented in

Stage 1: Applya two-dimensional (2D) window of size 3 × 3 to a center pixel with an 8-bit grayscale value denoted as

Stage 2: If 0 <

Stage 3: If

Case I: The window includes pixels with values that are not exclusively 0 or 255. Then, find the adaptive edge of the remaining pixels and replace _{ij} with its adaptive value.

Case II: The window includes pixels with values that are only 0, 255, or both. Then, the center pixel may be either zero or 255; again this is a small issue. Then, replace

Stage 4: Apply stages 1–3 to every pixel in the image.

The performance and operational characteristics of the proposed PLWF algorithm were compared to those of various other state-of-the-art noise-removal algorithms, including iterative pixel compression (IPC), and those based on the discrete cosine transform (DCT) and the DWT. To this end, the algorithms were applied to standard Lena and Cameraman8-bit grayscale images composed of 512 × 512 pixels. Salt and pepper noise having pixel values of 0 and 255 with equal probability was deliberately added to all images in proportions of 10% to 90% using MATLAB. For this, a window size of 9 × 9 was uniformly applied.

Parameter | Specification |
---|---|

Dataset | Natural and raw images |

Tools used | Matlab and XSG |

Number of images | 100 |

Languages | System C and HDL |

Device | Vertex-2 Pro FPGA |

The results of applying the proposed PLWF algorithm to the Lena and cameraman images in MATLAB are presented in

The noise-reduction performances of the algorithms compared were evaluated according tothe peak signal-to-noise ratio (PSNR) and mean square error (MSE), which are defined as follows [

where _{1}and _{2} represent the ground truth noise-free image and the denoised image, respectively, and

The PSNR and MSE values obtained by the various noise reduction algorithms for the Lena and cameraman images under different salt and pepper noise levels are listed in

Noise level | PSNR | MSE | ||||||
---|---|---|---|---|---|---|---|---|

DCT | DWT | IPC | PLWF | DCT | DWT | IPC | PLWF | |

10% | 42.39 | 42.46 | 46.46 | 0.02 | 0.02 | 0.02 | 0.02 | |

20% | 40.08 | 42.42 | 44.42 | 0.04 | 0.03 | 0.03 | 0.03 | |

30% | 38.84 | 40.96 | 42.96 | 0.05 | 0.05 | 0.05 | ||

40% | 37.77 | 39.78 | 41.78 | 0.06 | 0.06 | 0.06 | ||

50% | 36.70 | 38.86 | 40.86 | 0.08 | 0.08 | 0.08 | ||

60% | 36.08 | 38.27 | 40.27 | 0.09 | 0.09 | 0.09 | 0.09 | |

70% | 34.57 | 36.54 | 39.54 | 0.11 | 0.11 | 0.11 | ||

80% | 34.97 | 36.12 | 39.12 | 0.12 | 0.12 | 0.12 | ||

90% | 34.55 | 36.55 | 38.55 | 0.14 | 0.14 | 0.14 | 0.14 |

Other factors, such as the complexity of the hardware implementation and the power consumption of denoising algorithms, are equally important as the denoising performance. Therefore, we compare the percentages of the total area employed to implement the denoising algorithm and the percentage of total power consumed by that implementation in

Logic utilization | DCT | DWT | IPC | PLWF |
---|---|---|---|---|

Number of I/O | 131 | 131 | 130 | 130 |

Number of bonded IOBs | 117 out of 190 | 116 out of 190 | 111 out of 190 | 105 out of 190 |

Minimum period (ns) | 20.650 | 15.520 | 10.120 | 9.012 |

Minimum input arrival time (ns) | 21.750 | 17.510 | 11.821 | 10.25 |

Maximum output required time (ns) | 4.880 | 4.283 | 3.982 | 3.92 |

Maximum combinational path delay (ns) | 15.153 | 15.113 | 15.101 | 14.95 |

The present work addressed the need for developing image denoising algorithms with maximum denoising performance, speed, and efficiency on FPGA platforms by proposing a high-throughput fixed-point AEN filter architecture to denoise digital images in real time using a nonlinear modified PLWF technique. The denoising performance of the proposed denoising scheme was demonstrated to be superior to the denoising performances of IPC and those algorithms based on the DCT and DWT. Moreover, the hardware implementation of the proposed PLWF algorithm required less area and less power consumption than the other implementations considered, and the logic utilization and computational speed were both improved.

We thank LetPub (www.letpub.com) for its linguistic assistance during the preparation of this manuscript.