The fourth-generation (4G) and fifth-generation (5G) wireless communication systems use the orthogonal frequency division multiplexing (OFDM) modulation techniques and subcarrier allocations. The OFDM modulator and demodulator have inverse fast Fourier transform (IFFT) and fast Fourier transform (FFT) respectively. The biggest challenge in IFFT/FFT processor is the computation of imaginary and real values. CORDIC has been proved one of the best rotation algorithms for logarithmic, trigonometric, and complex calculations. The proposed work focuses on the OFDM transceiver hardware chip implementation, in which 8-point to 1024-point IFFT and FFT are used to compute the operations in transmitter and receiver respectively. The coordinate rotation digital computer (CORDIC) algorithm has read-only memory (ROM)-based architecture to store FFT twiddle factors and their angle generators. The address generation unit is required to fetch the data and write the results into the memory in the appropriate sequence. CORDIC provides low memory, delay, and optimized hardware on the field-programmable gate array (FPGA) in comparison to normal FFT architecture for the OFDM system. The comparative performance of the FFT and CORDIC-FFT based OFDM transceiver chip is estimated using FPGA parameters: slices, flip-flops, lookup table (LUTs), frequency, power, and delay. The design is developed using integrated synthesis environment (ISE) Xilinx version 14.7 software, synthesized using very-high-speed integrated circuit hardware description language (VHDL), and tested on Virtex-5 FPGA.

OFDM [

The ‘N’ point IFFT is applied on subcarriers symbols. The IFFT generates the transmitted samples. The IFFT output is passed to parallel to the serial converter, also known as the multiplexing operation to generate the serial stream. The cyclic prefix [

In the cyclic prefix, the samples are affected by inter-block interference (IBI). Therefore, it is required to remove the output corresponding to the cycle prefix. The output is given to serial to parallel converter or de-multiplexer. The output of the de-multiplexer is given to the ‘N’ point FFT block. The FFT has the received samples after the cyclic prefix and its transformation provides the output against subcarriers. The size of IFFT and FFT [

FFT is the core component of the OFDM system. The 2000/4000/8000-points FFT [^{4} FFT/IFFT architecture [

The OFDM is a type of digital transmission that encodes digital data onto multiple carrier frequencies. There are several platforms to realize the behavior of OFDM systems such as DSP processors, microcontrollers, and FPGA. The FPGA-based system can be reprogrammed with advanced features to meet the system requirements like frequency, optimal hardware, delay, memory, and power. It is found to be the best choice amongst all for OFDM implementation as it gives better flexibility to the program design at a low cost. OFDM is used in 4G and 5G wireless technology at the physical layer such as worldwide interoperability for microwave access (WiMAX), 3^{rd} generation partnership project (3GPP), long-term evolution

The architecture of the OFDM transmitter and receiver consists of IFFT and FFT respectively. The general equation of DFT for input sequence x(n) over a length ‘N’ is given by

In the same way, IDFT is given as

The term

Jack E Volder [

Here, x = Real component of the input vector, y = Imaginary component of the input vector, and z = Angle of the vector. The difference between the rotation and vector modes is in the formula for generating the signed d value.

For vector mode,

The description of the FFT algorithms and CORDIC is not given in the article. These are well-known algorithms, their description is also covered in Section-2.

An angle generator unit generates the intermediate phases of the twiddle factor angles generated by the rotation and pipelined architecture of the CORDIC algorithm. The demultiplexer takes the data from butterfly output, stores it in corresponding registers, and sends using multiplexers. In the FFT computation, researchers have used the multibank addressing scheme to realize the pipelined and parallel architecture of FFT, but these techniques will not be suitable for less memory hardware following the CORDIC algorithm. In their solution, the twiddle factor angle is not increasing and enriches the complexity in design for angle generator unit.

_{3}, n_{2}, n_{1}, n_{0}) for 32-point FFT. Each angle is the multiplication of the (2π/N), which is π, π/2, π/4, π/8 and π/16 for FFT (N = 2, 4, 8, 16, and 32) respectively. It is easily understood that the twiddle factors for 16-point FFT and 32-point FFT are increasing with a one-step increment of the clock signal.

S. No. | Twiddle Factor, |
---|---|

N = 2 | |

N = 4 | |

N = 8 | |

N = 32 | |

N = 1024 | |

Butterfly Counter | Stage 0 | Stage 1 | Stage 2 | Stage 3 | Stage 4 | |||||
---|---|---|---|---|---|---|---|---|---|---|

n3n2n1n0 | RAM Address |
Twiddle factor angle | RAM Address |
Twiddle factor angle | RAM Address |
Twiddle factor angle | RAM Address |
Twiddle factor angle | RAM Address |
Twiddle factor angle |

0000 | 0000 | 0 | 0000 | 0 | 0000 | 0 | 0000 | 0 | 0000 | 0 |

0001 | 0001 | π/16 | 1000 | 0 | 0100 | 0 | 0010 | 0 | 0001 | 0 |

0010 | 0010 | 2π/16 | 0001 | 2π/16 | 1000 | 0 | 0100 | 0 | 0010 | 0 |

0011 | 0011 | 3π/16 | 1001 | 2π/16 | 1100 | 0 | 0110 | 0 | 0011 | 0 |

0100 | 0100 | 4π/16 | 0010 | 4π/16 | 0001 | 4π/16 | 1000 | 0 | 0100 | 0 |

0101 | 0101 | 5π/16 | 1010 | 4π/16 | 0101 | 4π/16 | 1010 | 0 | 0101 | 0 |

0110 | 0110 | 6π/16 | 0011 | 6π/16 | 1001 | 4π/16 | 1100 | 0 | 0110 | 0 |

0111 | 0111 | 7π/16 | 1011 | 6π/16 | 1101 | 4π/16 | 1110 | 0 | 0111 | 0 |

1000 | 1000 | 8π/16 | 0100 | 8π/16 | 0010 | 4π/16 | 0001 | 8π/16 | 1000 | 0 |

1001 | 1001 | 9π/16 | 1100 | 8π/16 | 0110 | 4π/16 | 0011 | 8π/16 | 1001 | 0 |

1010 | 1010 | 10π/16 | 0101 | 10π/16 | 1010 | 4π/16 | 0101 | 8π/16 | 1010 | 0 |

1011 | 1011 | 11π/16 | 1101 | 10π/16 | 1110 | 4π/16 | 0111 | 8π/16 | 1011 | 0 |

1100 | 1100 | 12π/16 | 0110 | 12π/16 | 0011 | 4π/16 | 1001 | 8π/16 | 1100 | 0 |

1101 | 1101 | 13π/16 | 1110 | 12π/16 | 0111 | 4π/16 | 1011 | 8π/16 | 1101 | 0 |

1110 | 1110 | 14π/16 | 0111 | 14π/16 | 1011 | 4π/16 | 1101 | 8π/16 | 1110 | 0 |

1111 | 1111 | 15π/16 | 1111 | 14π/16 | 1111 | 4π/16 | 1111 | 8π/16 | 1111 | 0 |

The design of the OFDM transceiver chip is followed based on the bottom-up approach in which all the submodules of the transmitter and receiver are designed independently. The OFDM transceiver is designed in Xilinx Vivado 17.4 and synthesized on the Virtex-5 FPGA kit. The process of FPGA synthesis is depicted in

The design is simulated for a variable length of 8 point-1024-point FFT and IFFT. The simulation waveform for the successful data stream transfer is shown in

The hardware design report is extracted from the Xilinx software which consists of the information about the hardware used for the FPGA device and its design parameters such as the number of flip flops, the number of logic gates, memory utilization, number of slices, and LUTs. The designer has the right to decide the level of optimization required for the design. The hardware synthesis is done on Digilent manufactured Virtex-5 FPGA kit. The target FPGA device is xc5vlx20t-2-ff323, programmed in Virtex-5 FPGA kit. The timing parameter details are presented in terms of total path delay in nanoseconds (ns), input arrival time before clock pulse, frequency support (maximum), output time after clock pulse, and power consumption in mill watts (mW).

S.No | FFT/IFFT |
Slices | Flip-Flops | LUTs | Frequency |
Delay (ns) | Power (mW) |
---|---|---|---|---|---|---|---|

OFDM |
8 | 152 | 256 | 35 | 135.00 | 12.08 | 64.00 |

16 | 210 | 315 | 50 | 146.00 | 13.10 | 68.20 | |

32 | 345 | 405 | 58 | 175.00 | 14.24 | 75.16 | |

64 | 450 | 496 | 72 | 195.00 | 15.19 | 78.21 | |

128 | 615 | 720 | 115 | 214.00 | 17.10 | 81.30 | |

256 | 810 | 915 | 185 | 225.00 | 20.80 | 92.15 | |

512 | 1218 | 1310 | 205 | 230.00 | 21.40 | 116.32 | |

1024 | 1500 | 1625 | 220 | 235.00 | 25.00 | 132.10 | |

OFDM |
8 | 124 | 212 | 32 | 148.00 | 10.51 | 56.15 |

16 | 186 | 289 | 46 | 152.00 | 12.20 | 60.50 | |

32 | 314 | 368 | 52 | 186.00 | 13.50 | 64.17 | |

64 | 412 | 410 | 68 | 205.00 | 13.95 | 69.23 | |

128 | 575 | 650 | 110 | 220.00 | 15.19 | 72.16 | |

256 | 750 | 820 | 175 | 245.00 | 18.20 | 75.12 | |

512 | 1018 | 1225 | 198 | 275.00 | 19.41 | 89.10 | |

1024 | 1275 | 1575 | 205 | 295.00 | 22.00 | 104.25 |

S.No | FFT/IFFT |
Slices | Flip-Flops | LUTs | Frequency |
Delay (ns) | Power (mW) |
---|---|---|---|---|---|---|---|

OFDM |
8 | 430 | 510 | 98 | 192.00 | 18.10 | 110.50 |

16 | 620 | 715 | 124 | 210.00 | 19.20 | 117.25 | |

32 | 917 | 1034 | 145 | 276.00 | 20.43 | 145.20 | |

64 | 1220 | 1310 | 196 | 292.00 | 21.76 | 164.12 | |

128 | 1575 | 1650 | 315 | 310.00 | 23.50 | 195.18 | |

256 | 2276 | 1925 | 458 | 316.00 | 26.10 | 251.90 | |

512 | 3025 | 2520 | 560 | 325.00 | 27.98 | 310.39 | |

1024 | 4100 | 3225 | 610 | 356.00 | 32.00 | 400.50 | |

OFDM |
8 | 375 | 412 | 76 | 215.00 | 16.20 | 95.16 |

16 | 498 | 650 | 115 | 245.00 | 17.98 | 109.10 | |

32 | 720 | 945 | 124 | 298.00 | 18.20 | 135.18 | |

64 | 1005 | 1157 | 162 | 315.00 | 19.45 | 155.29 | |

128 | 1240 | 1435 | 298 | 342.00 | 21.50 | 167.21 | |

256 | 1972 | 1620 | 360 | 356.00 | 25.00 | 210.71 | |

512 | 2812 | 2100 | 486 | 376.00 | 24.36 | 255.40 | |

1024 | 3550 | 2835 | 515 | 400.00 | 30.00 | 315.00 |

Sood et al. [