The design of a three-input logic circuit using carbon nanotube field effect transistors (CNTFETs) is presented. Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices, which is why this design is so popular, and it also reduces chip area, both of which are examples of circuit overheads. The proposed module we have investigated is a triple-logic-based one, based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values, as well as comparisons of the design working with various load capacitances. Comparing the proposed design with the existing design, the delay times was reduced from 66.32 to 16.41 ps, i.e., a 75.26% reduction. However, the power dissipation was not optimized, and increased by 1.44% compared to the existing adder. The number of transistors was also reduced, and the product of power and delay (

The analysis of digital circuits is accomplished using dual-valued logic, i.e., 0 and 1, T and F in Boolean arithmetic. Multivalued logic (MVL) can be matched with the classical arithmetical modification of finite variables [

Carbon nanotubes (CNTs) are huge cylindrical molecules made up of a hexagonal arrangement of hybridized carbon atoms that can be made by rolling up a single sheet of graphene single-walled carbon nanotubes (SWCNTs).

CNTs have received more specific attention in the field of electronics because of their structure and excellent physical properties [

The paper is arranged as follows: Section 2 discusses carbon-based nano-type field effect transistors (FETs) and their suitability for three-input logic; Section 3 describes three-input logic itself; Section 4 describes the proposed three-input logic half adder; and, finally, Section 5 discusses the conclusions drawn from the results of our study.

“Simple and efficient design, reduced memory and inner connectivity, reduced on-chip area, serial and parallel transfer of data, increased potential for maximizing speed, decreased activity of switching, and applications of types of mathematical and Boolean functions on a single chip are all general uses of MVL” [

The carbon atom distance of each and every nearby atom is given as _{0} = 0.142 nm. A schematic diagram of a CNTFET is shown in

We have _{0} = 2.49 Å for the carbon-to-carbon distance and

Three input logic CNTFETs were employed in this application.

The fundamentals of ternary logic and how it is represented in terms of voltage levels may be represented by a few input logic gates that can be used to create adder circuits. The various ternary half-adder (THA) design implementations are evaluated and discussed below. Some design options use ternary logic gates (decoder-encoder), a combination of ternary and binary logic, multiplexers, transmission gates, and other techniques [

In the proposed design, a simple approach is considered for designing an efficient adder, and this approach is based on two-output/three-input logic to a binary decoder circuit. In an adder, the generation of sum and carry reduces the circuit’s complexity.

In the proposed design, A and B are the decoders, and if we allow a single input to a decoder, it will have multiple outputs. In that respect, A and B, which are inputs for the decoder, and the sum and carry circuits, are the operational circuits through which the sum and carry outputs are received. The proposed design for the decoder is rearranged by connecting 1-input and 2-output three-input logic to the dual-input logic decoder. These binary-decoded outputs are used for calculating the values (

From

For single inputs, dual outputs can be seen in

A | B | Sum | Carry | A1 | A0 | B1 | B0 | SUM2 | Cm | ||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|

0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 |

0 | 1 | 1 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | 2 | 0 | 2 |

0 | 2 | 2 | 0 | 0 | 0 | 2 | 2 | 0 | 2 | 2 | 0 | 0 | 2 |

1 | 0 | 1 | 0 | 0 | 2 | 0 | 0 | 2 | 0 | 0 | 2 | 0 | 2 |

1 | 1 | 2 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 2 | 0 | 0 | 2 |

1 | 2 | 0 | 1 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 2 | 0 |

2 | 0 | 2 | 0 | 2 | 2 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | 2 |

2 | 1 | 0 | 1 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 2 | 0 |

2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 0 | 0 | 2 | 2 | 0 |

Input | Output | |
---|---|---|

(A) | (A1) | (A0) |

0 | 0 | 0 |

1 | 0 | 2 |

2 | 2 | 2 |

Input | Output | |
---|---|---|

(B) | (B1) | (B0) |

0 | 0 | 0 |

1 | 0 | 2 |

2 | 2 | 2 |

If we go with a three-input logic circuit, the signals analyzed under the three modes, low, medium, and high, can be taken as 0, 1, and 2, respectively. A0 and A1 are the decoder circuit outputs for the three-input signal A (

The sum is just 2 for the combinations A1, A0 and B1, B0, namely, (0, 0, 2, 2), (0, 2, 0, 2), and (2, 2, 0, 0). The same is underlined in

By using

The results obtained from these dual circuits form a dual input to the three-input encoders, through which the three-input logic output can be observed. The circuit for the encoder in shown in

As listed in

From the waveform, it can clearly be seen that, for inputs (AB) = (00), Sum and Carry are (00), and for input A(0.5) and input B(0.5), Sum is 2 and Carry is 0, and the process follows for the different combinations of the waveform. According to

Circuit | Transistor count | Voltage (V) | Delay (ps) | Power (µW) | PDP × 10^{−15} (J) |
---|---|---|---|---|---|

Lombardi [ |
134 | 1 | 66.32 | 1.60 | 0.106112 |

Proposed (HA) | 66 | 1 | 16.41 | 3.04 | 0.0498053 |

Load capacitance (fF) | T-1 (ps) | T-2 (ps) | T-3 (ps) | T-4 (ps) | Average delay (ps) |
---|---|---|---|---|---|

0.5 | 30.697 | 19.741 | 23.067 | 16.652 | 22.54 |

1 | 40.374 | 24.151 | 32.679 | 20.497 | 29.43 |

1.5 | 49.82 | 28.546 | 42.272 | 24.218 | 36.21 |

2 | 59.501 | 32.996 | 51.662 | 27.91 | 43.02 |

2.5 | 69.243 | 37.434 | 61.336 | 31.59 | 49.90 |

3 | 78.306 | 41.889 | 70.798 | 35.221 | 56.55 |

3.5 | 88.358 | 45.974 | 80.619 | 38.77 | 63.43 |

4 | 97.573 | 50.923 | 89.604 | 42.103 | 70.05 |

4.5 | 107.22 | 55.674 | 99.509 | 45.096 | 76.87 |

5 | 117.04 | 60.293 | 109.43 | 47.648 | 83.60 |

Load capacitance (fF) | Power dissipation (µW) |
---|---|

0.5 | 3.38 |

1 | 3.73 |

1.5 | 4.09 |

2 | 4.44 |

2.5 | 4.77 |

3 | 5.12 |

3.5 | 5.47 |

4 | 5.81 |

4.5 | 6.17 |

5 | 6.49 |

Load capacitor (fF) | Power dissipation (µW) | Average delay (ps) | PDP × 10^{−16} (J) |
---|---|---|---|

0.5 | 3.38 | 22.54 | 0.761852 |

1 | 3.73 | 29.43 | 1.09774 |

1.5 | 4.09 | 36.21 | 1.48099 |

2 | 4.44 | 43.02 | 1.91009 |

2.5 | 4.77 | 49.90 | 2.38023 |

3 | 5.12 | 56.55 | 2.89536 |

3.5 | 5.47 | 63.43 | 3.46962 |

4 | 5.81 | 70.05 | 4.06991 |

4.5 | 6.17 | 76.87 | 4.74288 |

5 | 6.49 | 83.60 | 5.42564 |

A novel three-input logic-based adder using CNTFETs is described in this paper. The major function of the adder is the lowering of the CNTFET threshold voltage, and a novel two-valued diameter (