There are numerous goals in next-generation cellular networks (5G), which is expected to be available soon. They want to increase data rates, reduce end-to-end latencies, and improve end-user service quality. Modern networks need to change because there has been a significant rise in the number of base stations required to meet these needs and put the operators’ low-cost constraints to the test. Because it can withstand interference from other wireless networks, and Adaptive Complex Multicarrier Modulation (ACMM) system is being looked at as a possible choice for the 5th Generation (5G) of wireless networks. Many arithmetic units need to be used on the hardware side of multicarrier systems to do the pulse-shaping filters and inverse FFT. The main goal of this study is to adapt complex multicarrier modulation (ACMM) for baseband transmission with low complexity and the ability to change it. We found that this is the first reconfigurable architecture that lets you choose how many subcarriers a subband has while still having the same amount of hardware resources as before. Also, under the new design with a single selection line, it selects from a set of filters. The baseband modulating signal is evaluated and tested using a Field-Programmable Gate Array (FPGA) device. This device is available from a commercial source. New technology outperforms current technology in terms of computational complexity, simple design, and ease of implementation. Additionally, it has a higher power spectrum density, spectral efficiency, a lower bit error rate, and a higher peak to average power ratio than existing technology.

Recent field tests of 5G wireless communication have been conducted. 5G use cases are divided into massive Machine Type Communications (mMTC), enhanced Mobile Broadband (eMBB), and Ultra-reliable and Low Latency Communications (uRLLC) [

However, choosing a pulse-shaping filter is critical in UFMC to limit sidelobe power to adjacent subbands. This filter’s sidelobe fall rate is extraordinarily sluggish (0 dB/octave), resulting in significant spectrum leakage to neighbouring subbands [

Nowadays, [

The following are the present work’s significant contributions.

We want to develop a programmable baseband UFMC transmitter. We create a prototype of the suggested design and test it on a commercially available FPGA chip.

The maximum number of subcarriers that may be employed in the proposed architecture is 2(d-1), which equals the architecture’s data length. Use more than one subcarrier per subband for the UFMC transmitter.

Using base-band modulation, we investigate how the closeness of an approximate and the comfort level with truncation are affected by a fixed-size representation of the data-path width.

In fourth-generation broadband systems that have long depended on Orthogonal Frequency Division Multiplexing (OFDM), some of its drawbacks have spurred academics to examine other modulation methods that might improve global performance in the next generation [

By copying the final part of the signal at the beginning (cyclic prefix), OFDM reduces Inter-Symbol Interference (ISI) and makes the signal more resistant to channel delays Fast Fourier transform (FFT). Although OFDM is effective in most situations, it is not always easy to use.

Out-of-band radiation is the most severe flaw of OFDM, causing a lot of noise. Each subcarrier’s waveform is Sinc shaped. This type produces enormous secondary lobes. These lobes extend beyond the data transmission frequency range, resulting in worse global spectral efficiency. The secondary lobes of OFDM-Sincs are likewise relatively strong, emphasizing the requirement for accurate synchronization. Symbol mismatches destroy orthogonality and accentuate secondary lobe effects. A more extended cyclic prefix may help reduce interference but at a cost.

Recently, various modulation techniques have addressed obstacles such as high Peak to Average Power Ratio (PAPR) and phase and frequency noise susceptibility [

Recently, interest in Filter Bank Multi-Carrier modulation (FBMC) as a viable alternative to OFDM has increased significantly. FBMC is an improvement, particularly in spectrum efficiency and severe time restrictions. As with OFDM in general, each sub-carrier is filtered to minimize side-lobes and inter-carrier interference and the out-of-band effect of the global allotted bandwidth. As a result, the CP is not required, allowing for high data rates but complicating support for Multiple-Input and Multiple-Output (MIMO) systems. Due to the massive size of the filter, short-term transmissions are inefficient. The primary advantage of FBMC is the overlapping of surrounding subcarriers, which makes it resistant to synchronization problems [

Unlike FBMC, which filters individual OFDM sub-carriers, Universal-Filtered Multi-Carrier filters groups of sub-carriers. Unlike the FBMC filter, the length of the filter may be reduced by grouping sub-carriers. Each group receives its own IFFT, and the output is filtered identically (with the same filter, or even different filters can be applied if desired). As seen in

The simplicity and cheap cost make it an excellent choice for next-generation cellular networks, but complicated multicarrier modulation methods need that signals sent be genuine and positive. Because OFDM has inherent complex values, standard OFDM cannot be employed. To maintain the primary properties inherent in the original modulation while transmitting just a single actual component, many OFDM modifications have been proposed in recent years. If Hermitian Symmetry (HS) is applied to the inverse Fourier transform’s (IFFT/FFT) input, the output is real, but it requires twice the number of IFFT/FFT points in transmission and reception, which increases computational complexity, demands more power, and necessitates larger chip dimensions. This procedure has traditionally been followed. In order to limit negative magnitudes, many strategies have been suggested. These include either adding the equivalent DC bias to increase global power or simply clipping negative values to zero, which results in undesirable noise. Other approaches, such as the Hartley transform, have been proposed to avoid the needless IFFT and FFT computations. This transform, however, has the peculiarity of working in real space while restricting the input modulations to only being real, preventing us from using high-density constellations like M-ary Quadrature Amplitude Modulation (M-QAM). Sequentially, modern methods that split and transmit the complex-valued OFDM’s real (Re) and imaginary (Im) portions have achieved intriguing results.

As described in [

The physical layer candidates are compared against 5G as part of the project. Because the 5G standard hasn’t been finalized, it uses a variety of modulation methods. OFDM, FBMC, and UFMC modulation schemes are compared here. Simulating these modulations with an FFT length N = 512 and Bits per Subcarrier = 4 is necessary to compare. Periodograms of OFDM and UFMC baseband signals are shown together in

Output parameters | BER | SNR | PAPR |
---|---|---|---|

UFMC (LF-43) | 0.0025 | 15 dB | 7.6004 |

FBMC (SF-4) | 0 | 15 dB | 14.1016 |

OFDM (CP-43) | 0 | 15 dB | 7.3036 |

Notes: **Length of Filter (LF); Spreading Factor (SF); Cyclic Prefix (CP)

The Fast Fourier Transform (FFT) is a discrete Fourier transform variant of the Discrete Fourier Transform (DFT). By lowering the time and effort necessary to calculate the DFT, the Fast Fourier Transform (FFT) decreases its computational complexity. The butterfly diagram in

This computing technique improvement results in increased processing components while retaining the first-in, first-out process size. Parallel pipelined FFT requires less electricity due to lower frequency. FFT uses improved Coordinate Rotation Digital Computer (CORDIC) to build FPGA [

The performance of the proposed MAFA-RICO may be investigated utilizing an FFT-based design on FPGAs [

The MAFA-RICO technique [

Instead of having a specific model, inexact systems may be used to prepare all contract portions more efficiently. Because low-execution setups are more likely to include known faults, the superior design may use theoretical findings rather than idealized outcomes. Compared to a unit’s efficiency and inaccurate operation’s speed was more susceptible to competence than accuracy [

The proposed MAFA1 is based on the logic formulations in

_{in}) are allocated a carry output to reduce node capacitance and speed up the carry propagation channel computations. There is less carry delay in the MAFA1 design than the overall output delay. Errors in carry output result in incorrect values being formed instead of correct values being produced overall, decreasing the error distance value to a value of 1, as seen in

Inputs | MAFA1 | ||||
---|---|---|---|---|---|

A_{in} |
B_{in} |
C_{in} |
Carry | Sum | Error |

0 | 0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 0 | 1 | 0 |

0 | 1 | 0 | 0 | 1 | 0 |

0 | 1 | 1 | |||

1 | 0 | 0 | |||

1 | 0 | 1 | 1 | 0 | 0 |

1 | 1 | 0 | 1 | 0 | 0 |

1 | 1 | 1 | 1 | 1 | 0 |

An approximation full adder-II based on a four-unit multiplexer (MAFA2) is described in _{in}” input. If Approximate FA Carry equals “0,” the Approximate HA Sum output is chosen; otherwise, the Approximate FA Sum output is set to “C_{in}.”

There are seven fundamental logic gates in the proposed MBAFA-II logic, as shown in

Inputs | MuxAFA-II | ||||
---|---|---|---|---|---|

A_{in} |
B_{in} |
C_{in} |
Carry | Sum | Error |

0 | 0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 0 | 1 | 0 |

0 | 1 | 0 | 0 | 1 | 0 |

0 | 1 | 1 | |||

1 | 0 | 0 | 0 | 0 | 0 |

1 | 0 | 1 | |||

1 | 1 | 0 | 1 | 0 | 0 |

1 | 1 | 1 | 1 | 1 | 0 |

The accurate 16-bit MAFA1 calculation makes use of a typical RCA-based structure. At the same time,

The proposed MAFA-RICO pseudocode rapidly computes the sine/cosine of the input angle (

i | Rotation angle (θ |
σ1 | σ2 | σ3 | σ4 |
---|---|---|---|---|---|

0 | 0–10 | 1 | 0 | 0 | 0 |

1 | 10.1–20 | 1 | 0 | 0 | 1 |

2 | 20.1–40 | 1 | 0 | 1 | 0 |

3 | 40.1–60 | 1 | 1 | 0 | 0 |

4 | 60.1–80 | 1 | 1 | 0 | 1 |

5 | 80.1–90 | 1 | 1 | 1 | 0 |

When computing sine/cosine, the proposed MAFA-RICO (low power multiplexed approximate adder-based repeated iteration CORDIC) algorithm utilizes an arc-shaped route rotation (see _{out}, n_{out}, and m_{in}, n_{in} are defined as inputs, although the input and output vector is supplied independently. Iterations of component scaling are consistent with sl_ft, and micro-rotation of the path is μ_{0,} μ_{1,} μ_{2,} μ_{3,} and μ_{4}.

Accurate estimation _{1}, μ_{2}_{3}_{θ} present. Shift logic is used to accomplish microrotation and non-iterative reasoning to compute sin and cos. _{1}

It has also been found and registered that micro-rotation may be used for _{1}_{2}

Logic for shifting levels must be specified in advance to determine the complexity to be shifted by the _{out}_{out}_{1}_{2}

The proposed approximate inaccurate technique Non-Iterative function eliminates the need for iteration on information 0, 1, and 2. It holds _{out} and n_{out}, then calculate

The following are the MAFA-RICO-approximated architectural functions [

_{1} and μ_{2} for generating shifts.

It is necessary to rotate the input vector 3 (m_{in}, n_{in}) twice, by a 10° angle, to arrive at the values of m_{out} and n_{out,} where m_{in }= 1 and n_{in }= 0. In a single rotation, the output vector m_{out1}, n_{out1} are represented by

where, _{3} = ± 1. The _{out} and n_{out} that result from satisfying the above requirements

An illustration of an input-to-output relationship is shown in _{out}, n_{out}), Shift 1, and Shift 2 as commitments to iteration

where, _{0}, μ_{1}_{2}

Any input angle tθ, sine/cos calculation may be handled by the MAFA-RICO architecture, which has been proposed as a nonexclusive CORDIC solution.

The Approximate CORDIC technique and the FFT enhancement for biomedical signal processing are designed using Xilinx 14.5 ISE, which simulates and synthesizes them. There are three assessment stages for our proposed FFT architecture: design, implementation, and signal processing. Initially, the MAFA-RICO FFT architecture’s sub-blocks are evaluated regarding the number of adders, registers, and comparators they need. The findings are summarized in

Parameters | Exact_RICO | APRICO | Proposed 1 | Proposed 2 |
---|---|---|---|---|

Registers | 9392 | 8851 | 9057 | 8793 |

Comparators | 320 | 320 | 320 | 320 |

Multiplexers | 320 | 320 | 1344 | 1344 |

Add/Sub | 128 | 128 | 128 | 128 |

Time (ns) | 16.643 | 19.157 | 29.377 | 13.783 |

Design | FPGA board | No. of slice registers | No. of slice LUTs | No. of LUT-FF pairs | Number of bonded IOBs | Time (ns) | Frequency |
---|---|---|---|---|---|---|---|

Proposed 1 | Virtex 6 | 9057 | 4360 | 7253 | 544 | 29.377 | 331.7 MHz |

Proposed 2 | Virtex 6 | 8793 | 3745 | 7092 | 544 | 13.783 | 331.7 MHz |

Approx._RICO | Virtex 6 | 8851 | 4962 | 7529 | 544 | 19.157 | 276.3 MHz |

Exact_RICO | Virtex 6 | 9392 | 4783 | 7134 | 544 | 16.643 | 276.3 MHz |

Co-FFT (Ref. [ |
Zynq7000 | 3666 | 4332 | 5242 | 49 | 1.5 GHz | |

Co-FFT (Ref. [ |
Spartan-6 | 475 | 2177 | 418 | 138 | 82.7 MHz | |

R16CO FFT (Ref. [ |
Virtex-7 | 11, 302 | 11 | 230 MHz | |||

UMA-FFT (Ref. [ |
Virtex 5 | 1295 | 2350 | 8.02 | 253.7 MHz |

Design | RICO FFT | APRICO FFT | Proposed 1 | Proposed 2 | UE-FFT (Ref. [ |
VM-CLA (Ref. [ |
---|---|---|---|---|---|---|

FFT points (N) | 256 | 256 | 256 | 256 | 126 | - |

Data length | 16-bit | 16-bit | 16-bit | 16-bit | 16-bit | 32-bit |

Technology | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm | 180 nm |

Delay (ps) | 11096 | 14018 | 10979 | 10681 | 2.2772 | 80.4 |

Area (um2) | 93341 | 92270 | 85504 | 73350 | 9562 | 70, 385 |

Power (mW) | 4.831 | 3.001 | 2.64 | 2.912 | 3.462 | 159.246 |

ADP (μm^{2}.ns) |
1035.711 | 1293.44 | 938.748 | 783.451 | - | 5, 663, 880 |

PDP (mw.ns) | 53604.77 | 42068.02 | 28984.56 | 31103.07 | - | 11208533.30 |

In this work introduces a baseband UFMC modulator with a hardware-efficient reconfigurable architecture. The proposed architecture contains a variety of pulse-shaping filters that may select depending on the desired FOM, and there are no substantial changes in hardware resources necessary to choose the number of subcarriers in each subband. The experimental baseband signal validates the computations. In addition, we evaluated and compared the error bound of the suggested design because of its reconfigurability, hardware efficiency, and reuse of several hardware components. The proposed reconfigurable design for the UFMC modulator is ideally suited for 5G systems. UFMC systems may benefit from greater operating frequency by using the proposed architecture’s data and process level pipelining. When we examined parameters such as PAPR, BER, Spectral Density, and Spectral Efficiency, we were able to assess the effectiveness of the modulation schemes. This reconfigurable architecture might be enhanced by applying the modulation methods to distinct wireless communication channels. We want to enhance our proposed design for high-speed reconfigurable multicarrier systems.

The authors received no specific funding for this study.

The authors declare that they have no conflicts of interest to report regarding the present study.